Design and
Implementation of an Ultra High-Speed WLAN: Concept, SoC-Implementation and
Demonstrator (WIGWAM-IHP)
Responsible:
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IHP
Prof. Rolf Kraemer
Dr. Eckhard Grass
Im Technologiepark 25
D-12589 Frankfurt (Oder) |
Approach:
The following main aspects will be investigated:
- Radio front-end architectures and implementations for
60 GHz transceiver:
The focus is on the design and implementation
of a 60 GHz transceiver using SiGe:C BiCMOS technology.
- Baseband processor for ultra-high data rates up to 1
Gbit/s:
We will investigate OFDM-baseband
architectures which support data rates up to 1 Gbit/s at limited bandwidth.
The architectures have to facilitate a cost efficient implementation of the
baseband unit. Flexibility and adaptability of the designs should allow the
customization of the baseband processor for a wide range of applications.
Important topics are the definition of efficient and robust strategies for
synchronization and channel estimation.
- Ultra-high throughput protocol processor:
The desired data rate of 1 Gbit/s requires
very efficient algorithms and architectures for the protocol processor. Based
on high-level algorithmic models we will identify operations that should be
executed in hardware. For the implementation of the protocol processor we will
focus on standard microcontrollers supported by customized hardware
accelerator.
- System-on-Chip integration:
The price of products can be reduced when as
many components as possible are integrated into a single chip. This brings
about the problem of interference between digital and analog components (EMC,
crosstalk). Using Globally Asynchronous, Locally Synchronous (GALS) design
techniques can contribute reducing problems associated with EMC and crosstalk.
Furthermore clock distribution and RTL-level synchronization problems are
alleviated. We want to investigate and quantify the effects GALS techniques
have on a complex circuit block like the baseband processor.
- Demonstrator design and implementation.
Only a Demonstrator can convince suppliers and
users of a new technology and its benefits. Therefore we have committed
ourselves to implementing a complete demonstrator, transmitting data at 1 Gbit/s
in the 60 GHz band. It will consist of own developed modules as well as
commercially available components. By defining clear interfaces between the
major blocks, we will give our project partners the opportunity to test their
own developed
components using our demonstrator.
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